In a recently published monograph ("Polysilicon Emitter Bipolar Transistors", A. K. Kapoor et al., editors, IEEE Press, 1989, page 3) can be found the following: "Bipolar technology has always been the technology of choice when high performance (high speed and high driving ability) is the prime concern. Emitter coupled logic (ECL) is a typical and familiar example. Despite the distinctively superior electrical characteristics displayed by bipolar transistors compared with MOSFETs . . . , bipolar chips had the long-standing disadvantages of high power consumption and low packing density. Polysilicon emitter transistor (PET) technology has emerged now as the cutting-edge bipolar technology dramatically overcoming the traditional disadvantages. The PET has ushered bipolar technology into VLSI . . . ".
PETs are well known to those skilled in the art. See, for instance, the article by C. R. Selvakumar in the above cited monograph (pp. 3-16), which is incorporated herein by reference. A version of PETs that is currently of particular interest comprises a highly doped polysilicon layer, overlying the base, that serves both as a diffusion source for shallow (emitter/base) junction formation and as a means for contacting the shallow emitter region. Typically, after the conventional base processing and emitter window opening steps, undoped polysilicon is deposited, subsequently implanted with a precise amount of arsenic atoms, followed by a heat treatment to anneal out damage and to form the emitter/base junction.
As reviewed in the above cited article on page 4, one of the crucial steps in PET manufacture is the treatment given to the wafer just prior to the deposition of the polysilicon. The many different prior art treatments can be roughly grouped into two categories. The first one involves an intentional or unintentional growth of a thin oxide layer (0.2 to 2 nm). The second involves the growth of a thin thermal nitride layer (about 1.0 to 1.5 nm). The "interface" treatment is important because it can have a pronounced effect on the electrical characteristics of PETs.
One of the advantages of PETs is their typically high current gain, as compared to conventional metal emitter transistors. Many different theories have been put forward to explain the origin of the enhanced current gain. For a concise review, see the above cited article, especially pages 5-12. Among the proposed mechanisms invoked are smaller bandgap narrowing in the polysilicon; the presence of a tunneling layer between the polysilicon and the underlying single crystal Si; smaller hole mobility in the polysilicon, as compared to the single crystal Si; and dopant pile-up at the interface. As summarized by Selvakumar (op. cit.), the theoretical models can be grouped under two categories, namely a) those based on barrier theories involving either tunneling or thermionic emission over i) an oxide barrier or ii) a doping barrier due to pile-up at the interface, and b) those that are based on the carrier transport through the polysilicon film.
Despite the plethora of proposed mechanisms, none of the known theoretical models can account for all the experimental observations. Thus it is clear that theory can not yet provide reliable guidance to the worker who seeks to improve PET characteristics.
As stated by Selvakumar (op. city. page 12)" . . . a thin interfacial oxide layer helps to obtain very high current gains in PETs which could be traded . . . for low base resistances by doping the base more heavily. Unfortunately, the interfacial oxide layer impedes the flow of majority carriers and, hence, gives rise to a higher emitter resistance. Therefore PETs with as thin an oxide layer as possible are often sought in practice . . . ". Decreased base resistance would be highly desirable because it can result in higher operating speed. Increased emitter resistance is undesirable because it results in reduced speed and higher power consumption.
A consequence of the importance of (difficult to control and reproduce) interface conditions in PETs is the known difficulty in obtaining gain uniformity for devices on a given wafer, and/or between wafers. This is a severe drawback in VLSI and has caused designers to sacrifice potentially available gain.
In view of the importance of PETs it would be very desirable to have available a method of making PETs that can reliably result in devices with uniformly improved characteristics, e.g., in PETs with decreased base resistance but substantially unchanged current gain and emitter resistance, all as compared to an analogous prior art PET. This application discloses such a method.